This invention relates to memory transfer engines in semiconductor chips.
As the demand for high performance microprocessors increases, efficient transfer of data to memory becomes increasingly important. One mechanism for efficient transfer to memory is indexed addressing, which enables different memory banks to be accessed. While one address may be specified in an instruction, different variables or controllers considered during address calculation determine the effective address where memory will be written.
In order for efficient memory transfer to occur, it is also necessary to be able to quickly identify available memory. As shown below, the prior art offers various approaches to this problem.
U.S. Pat. No. 5,249,280 shows a method of index addressing six memory banks. In a first method, a number from 0 to 5, which corresponds to one of the memory banks, is stored in an index register using a 4-bit subfield. During an effective address calculation using index-addressing mode, a 16-bit logical offset stored in an offset register is appended to the index register to form a 20-bit address specifying a specific memory bank. If sequential memory accesses cross memory banks, the number stored in the index register will be automatically incremented to the next memory bank in sequential order.
U.S. Pat. No. 5,813,040 shows a CAM memory in which a controller includes a hardware-encoded bit map that tags locations containing valid data with status bits, read/write control logic, and search logic for selecting available memory locations. When responding to write instructions, the controller will use a linear search of the memory space to look for and stop at the first available memory location. Data is then written into the found memory location and a status bit is set which indicates that the memory location is no longer available for writing. This status bit is reset when either the memory location is read or the system is reset.
U.S. Pat. No. 5,937,186 shows a mechanism for identifying the next available memory space to store current register data when responding to an interrupt routine. This space is identified by reading the stored information of the previously-serviced routine. Each time a routine is serviced, header information is added to the current subroutine data. The header information includes a pointer to the previous subroutine data and the next available memory space.
It is an object of this invention to locate available memory space by determining which controllers associated with available memory are inactive.
Another object of this invention is to activate inactive memory controllers by assigning tasks to them by using indexed addressing.
A semiconductor chip""s memory transfer engine (MTE) consists of a plurality of memory transfer controllers (MTCs), each MTC having direct access to its associated plurality of dual port data memory (DPDM) registers and hardware registers. Each MTC can also access the DPDM registers and hardware registers associated with the other MTCs in the MTE.
The MTE has one hardware processor which is shared among the MTCs in a round-robin, time-sliced manner. When an executing MTC relinquishes control of the processor, an arbiter chooses the next MTC to control the processor from the MTCs that are ready to execute an instruction.
The index register (MX register), one of the MTC""s hardware registers, contains a value which, when considered with the address fields specified in MTC instructions, indicates which MTC""s data registers will be involved in the execution of an instruction. The MX register allows the MTC to access register banks of other MTCs.
An executing MTC can execute an instruction to determine the identity of an inactive MTC, which is associated with available memory space. The currently executing MTC""s MX register is loaded with an index to the inactive MTC. Using indexed addressing, the executing MTC activates the inactive MTC by writing to the inactive MTC""s hardware register. The activated MTC is now ready to execute its assigned task.